![]() ![]() Obviously, for the synopsys VCS to capture all of the waveforms of the design, one section of the AXI_OpenRISC_testbench will contain the following lines (in Verilog): Suppose that the name of the test bench module is : AXI_OpenRISC_testbench Suppose that the top level module of the developed RTL is called : AXI_OpenRISC_topĪnd we have developed a test bench, in which we have instantiated the AXI_OpenRISC_top unit and we have also created the required logic to stress this unit. ![]() Logic Simulation and Obtaining Switching Activity Statistics: ![]() During my descriptions I suppose that Synopsys VCS is used for logic simulation. In this writing I go through the details of how power estimation at RT level can be done using the Synopsys Design Compiler environment. The test bench developed by the designer for the logic simulation is indeed the workload imposed to the circuit and power will be estimated for this specific workload. Estimation of power consumption of an integrated circuit at RT level can be handy since it allows designers to obtain an approximate and yet accurate enough estimate on total power consumption of their design in a very short time.īasically, the designer runs the logic simulation for his pure RTL design and obtains the switching activity statistics for his circuit. ![]()
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